1. Field of the Invention
The present invention relates to a semiconductor memory test circuit and a method for the same. More particularly, it relates to a semiconductor memory test circuit and a method for the same which reduce the test time in testing a semiconductor memory.
2. Description of the Prior Art
Generally, to determine whether cells of a manufactured memory chip are a in Pass state or a in Fail state, assuming that the testing of every one cell is performed in a semiconductor memory, it takes a great deal of time to test a high-integration device, and the test cost increases. Accordingly, a parallel test has been used to reduce the test time.
The parallel test (pt) writes the same data to a plurality of cells and uses an exclusive OR circuit in a reading operation, thereby determining a Pass state xe2x80x9c1xe2x80x9d when the same data are read by the exclusive OR circuit, or a Pail state xe2x80x9c0xe2x80x9d when different data is read by the exclusive OR circuit.
A 3RD 64M Extended Data Out Dynamic Random Access Memory (EDO DRAM) performs a parallel test (pt) of 2Mxc3x9732Bit. For a parallel test of over 2Mxc3x9732Bit, the 64M EDO DRAM should consider a chip size according to an increase of a read/write data (RWD) line, thus the parallel test over 32Bit is not considered in the 64M EDO DRAM.
Here, unlike a parallel test performing a write/read operation by generally using only two input/output pads, the 3RD 64M EDO DRAM performs, as to a principle of the parallel test, a parallel test by using the same input/output pad as a normal operation as shown in the following TABLE 1, according to each construction.
The parallel test is started by enabling a signal xe2x80x9cptxe2x80x9d by a WCBR(/WE, /CAS Before /RAS) refresh, and exits by disabling a signal xe2x80x9cptxe2x80x9d by CBR(/CAS Before /RAS) refresh or ROR(/RAS only Refresh).
If the signal xe2x80x9cptxe2x80x9d is enabled from the WCBR mode, an address combination for driving a cell of 2Mxc3x9732Bit by the signal xe2x80x9cptxe2x80x9d is achieved from a Y-address buffer, has no correlation with each construction (x4/, x8/, x16), and is different in a 4K refresh or an 8K refresh.
In the case of an 8K refresh, the X-address ranges from X0 to X12 because of 8K=213, and addresses (Y8, Y9, Y10, Y11) among a plurality of Y-addresses are compressed by the signal xe2x80x9cptxe2x80x9d; thus the Y-address actually driving the Y-decoder ranges from Y0 to Y7.
In the case of a write operation, 32 data per one operation are loaded on a read/write data (RWD) line and are recorded on 32 cells.
In the case of a reading operation, one word line and one Y-input (Yi) per 8M block are enabled in one operation so that data of 4 cells are accessed to a global database (DB) line via 4-bit line pairs and are loaded on 32 RWD lines.
The Pass or Fail state of the data loaded on 32 RWD lines is determined by an exclusive OR circuit positioned to each pad, and the data loaded on 32 RWD lines are output to an I/O pad proper to each construction such as x4/,x8/,x6.
In the case of a 4K refresh, the X-address ranges from X0 to X11 because of 4K=212 as well as a previously compressed X12 address, addresses (Y8, Y9, Y10, Y11) among a plurality of Y-addresses are compressed by the signal xe2x80x9cptxe2x80x9d, and the following operation is the same as an 8K refresh.
In the parallel test, a write/read operation is achieved through two I/O pads, regardless of each construction such as xc3x974/, xc3x978/, xc3x9716, but this 3RD 64M EDO DRAM performs a parallel test through the same I/O pad as the construction. Also, in a reading operation, 32 data are not simultaneously compared by an exclusive OR circuit; only two data belonging to each I/O pad are logically compared by the exclusive OR circuit so that the 3RD 64M EDO DRAM can be tested by writing different data on each I/O pad.
Such a parallel test is shown in the following Table 2.
The parallel test (pt) such as that in the above Table 2 is made by reducing the number of column addresses in order to drive a manufactured product with xc3x9732Bit. By doubling the activation of a column address, the test speed proportionally doubles.
In the meantime, as the generation of a high-integration semiconductor memory device increases, the number of cells increases four times.
As a result, the test time also increases four times, thereby increasing the test time as well as the test cost.
For example, in case of a 64M DRAM, its test time is about four times of that of a 16M DRAM and 16 times of that of a 4M DRAM, and its test cost is also increased.
Assuming that 128M, 256M, and 1G DRAMs are manufactured in the future, the test time and the test cost will further increase.
In particular, in the case of a long-cycle disturbance test, it takes 64 msec per one cycle in an 8K refresh so that a test time of over 64 msecxc3x978K Row=512sec (i.e., 8 minutes and 32 seconds) is needed.
Also, in the case of a 4K refresh, it takes 64 msec per cycle, so that a test time of over 64 msecxc3x974K Row=256 sec (i.e., 4 minutes and 16 seconds) is needed.
In other words, since a test time of about 4-8 minutes per device is needed, the test time and the test cost will be continually increase in the mass-production of the devices.
Accordingly, the present invention is directed to a semiconductor memory test circuit and a method for the same that substantially obviate one or more of the problems due to the limitations and disadvantages of the related art.
It is an objective of the present invention to provide a semiconductor memory test circuit and a method for the same which achieve a new function by using a conventional parallel test signal, and to apply a test time reduction scheme to a long cycle disturbance test in a package test in order to correspond to an increasing test cost as the generation of devices increases in a high-integration semiconductor memory, thereby reducing the test time of a semiconductor memory device.
To achieve the above objective, a semiconductor memory test circuit includes a parallel test circuit for performing a parallel test when inputting a battery backup signal (bbu), a column address signal (cas5), a CAS before RAS signal (cbr), a write enable signal (ew), a power-up bar signal (pwrupb), and a row address signal (ras71); and a test mode circuit which is controlled by a combination between a parallel test signal (pt) and the battery backup signal (bbu) generated from the parallel test circuit and generates a test time reduction signal (ttrb), whereby the semiconductor memory test circuit compresses one least significant bit indicating a row address of a device in the case of a 4K refresh operation when the test time reduction signal (ttrb) is enabled, and compresses two least significant bits indicating a row address of a device in the case of an 8K refresh operation when the test time reduction signal (ttrb) is enabled.
A semiconductor memory test method includes the step of controlling a test time reduction signal (ttrb) by a combination of a parallel test signal (pt) and a battery backup signal (bbu), wherein the test time reduction signal (ttrb) compresses one least significant bit indicating a row address of a device performing a 4K refresh operation in the case of a 4K refresh operation, and compresses the two least significant bits indicating a row address of a device performing an 8K refresh operation in the case of an 8K refresh operation.
The parallel test circuit includes a high voltage generator for generating a high voltage by buffering an input signal; a RAS only refresh detector for generating a RAS only refresh signal by detecting an input RAS signal or an input CAS signal; and a parallel test signal generator for generating a parallel test signal by both the high voltage signal from the high voltage generator and the RAS only refresh signal from the RAS only refresh detector.
The test mode circuit includes a NAND gate which receives a parallel test signal and the battery backup signal generated from the parallel test circuit as an input and performs a NAND operation about them; a NAND gate latch which receives an output signal of the NAND gate and the parallel test signal as an input and generates a signal of xe2x80x9c0xe2x80x9d when the output signal of the NAND gate and the parallel test signal are xe2x80x9c1xe2x80x9d; and a buffer for buffering an output signal of the NAND gate latch.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objective and other advantages of the invention will be realized and attained by the structure particularly indicated in the written description and claims hereof as well as the appended drawings.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.